Fully integrated ultra wideband transmitter circuits and systems

ABSTRACT

Disclosed is a novel design of a fully integrated UWB transmitter. The transmitter includes a pulse generator, a pulse modulator, and an ultra-wideband drive amplifier. A new low voltage low power pulse generator circuit is disclosed which can be fully integrated in CMOS or BiCMOS process. This circuit includes a squaring stage, an exponential stage, and a second-order derivative stage. Based on this, PPM, BPSK and PAM pulse modulator circuits and system are disclosed. The modulated pulse is symmetrical second-order derivative Gaussian pulses with a bandwidth up to 5 GHz and having sufficient swing for UWB applications. An ultra-wideband driver amplifier is proposed to amplify the modulator output and drive the antenna. For the driver amplifier, common source resistor and inductor shunt feedback with current reuse technique is employed to achieve the ultra-wideband bandwidth, high gain, and providing matching for the antenna simultaneously.

BACKGROUND

The present invention relates to transmitter circuits and systems, andmore particularly to ultra wideband transmitter circuits and systems.

Ultra-wide band (UWB) is a new and promising technology for high speed,short range and portable wireless communication systems and devices. UWBtechnology enables new opportunities in the development of short rangeand high data rate wireless communication applications such as wirelessPersonal Area Network (PAN), interactive gaming, office networking andindoor communications.

The design of the building blocks of the UWB wireless transceiver isvery demanding due to its simultaneous requirements for ultra-widebandwidth, high speed, high throughput, low interference and low powerconsumption. Critical to operation is the generation of vary narrowpulses (typically 0.2-2 nano-seconds) onto which information ismodulated. It is extremely difficult to generate sub-nanosecond pulsesin pulse generator/modulator circuits whether the circuit be formedeither from discrete components due to interconnection discontinuities,and capacitive coupling between components, or in an integrated circuitdue to the low isolation and low current gain of the complementary metaloxide semiconductor (CMOS) or bipolar-complementary metal oxidesemiconductor (BiCMOS) processes.

Furthermore, the pulse generator/modulator output is often times too lowto drive the antenna, and accordingly a matching network is many timesnecessary to provide optimal impedance matching to the UWB antenna.Typically however, the matching circuit is not as broadband as the UWBspectrum (e.g., 3.1-10.6 GHz in the U.S), and thus power loss due toimpedance mismatch occurs over some part of the transmission band.Additionally, broadband matching networks are typically quite lossy, andthus provide diminishing returns on bandwidth versus output power.

Accordingly, a need exists for improved UWB transmitter circuits andsystems, and which are preferably capable of monolithic integrationusing CMOS or BiCMOS semiconductor processes.

SUMMARY

The present invention provides UWB transmitter circuits including aGaussian pulse generator, an ultra wideband modulator which is basedupon the Gaussian pulse generator design, and a driver amplifier. Themodulator circuit is configured to provide second-order derivativeGaussian pulses. The driver amplifier is used to provide gain and abroadband impedance matching between the modulator circuit andtransmitting antenna such that the modulated UWB pulse is transmittedwith high power and low distortion. The aforementioned circuits can beeither fabricated separately, or integrated into a UWB transmittercircuit, or alternately formed in a monolithic integrated circuit using,for example, CMOS or BiCMOS semiconductor processing.

The Gaussian pulse generator circuit, in an exemplary embodiment,includes a squaring stage, an exponential stage, and a second-orderderivative stage. The squaring stage includes a first transistor whichis configured to operate in the transistor's saturation region. Theexponential stage includes a second transistor coupled to the firsttransistor, the second transistor configured to operate in thetransistor's sub-threshold region. The second-order derivative stageincludes a capacitive-inductive network coupled to the secondtransistor, and an output terminal, wherein, when a load is coupled tothe output terminal, the real resistance of the load combines with thecapacitive-inductive network to provide a second order derivativeresponse.

The ultra wideband modulator circuit includes the above-describedGaussian pulse generator circuit and a modulation control circuit. Themodulator control circuit includes an input configured to receive acontrol signal and an output coupled to the Gaussian pulse generatorcircuit, whereby the modulation control circuit operates to modulate thebiasing condition of the exponential stage as a function of the controlsignal.

The design of the ultra wideband driver amplifier circuit includes aplurality of serial-coupled amplifier stages, each amplifier stagehaving parallel coupled first and second amplifier stage transistors anda feedback network. Each of the first and second amplifier stagetransistors having first, second and third terminals, whereby the firstterminals of the first and second amplifier stage transistors arecoupled together at a first node, and the third terminal of the firstamplifier stage transistor and the second terminal of the secondamplifier stage transistor are coupled together at a second node. Thefeedback network, which includes inductive and resistive elements, iscoupled between the first and second nodes.

The ultra wideband transmitter circuit includes the above-describedultra wideband modulator circuit and the driver amplifier circuit. In aparticular embodiment, the transmitter circuit is fabricated as anintegrated circuit using either a BiCMOS or CMOS semiconductor process.

These and other features of the invention will be better understood whenviewed in light of the following drawings and detailed description.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a circuit block diagram of a UWB transceiver inaccordance with an embodiment of the present invention.

FIG. 2 illustrates a Gaussian pulse generator circuit in accordance withan embodiment of the present invention.

FIG. 3A illustrates a circuit block diagram of an ultra widebandmodulator circuit in accordance with one embodiment of the presentinvention.

FIG. 3B illustrates an ultra wideband pulse amplitude modulator circuitin accordance with one embodiment of the present invention.

FIG. 3C illustrates an ultra wideband bipolar phase shift keyedmodulator circuit in accordance with one embodiment of the presentinvention.

FIG. 3D illustrates the performance of a BPSK modulator constructed inaccordance with the present invention.

FIG. 4 illustrates an ultra wideband driver amplifier circuit inaccordance with one embodiment of the present invention.

FIG. 5A illustrates a simplified block diagram a transmitter circuitconstructed in accordance with the present invention.

FIG. 5B illustrates the performance of an ultra wideband transmitterconstructed in accordance with the present invention.

For clarity, previously identified features retain their referenceindicia in subsequent drawings.

DETAILED DESCRIPTION OF SPECIFIC EMBODIMENTS

A fully integrated UWB transmitter is presented which includes a pulsemodulator, an ultra-wideband drive amplifier and an antenna. A lowvoltage, low power pulse generator circuit is presented which can befully integrated in CMOS or BiCMOS process. Based upon the fullyintegrated pulse generator circuit, new PPM, BPSK and PAM pulsemodulator circuits and system are constructed. The modulated pulse issymmetrical second-order derivative Gaussian pulses with a bandwidth upto 5 GHz and having sufficient swing for UWB applications. Theultra-wideband driver amplifier is used to amplify the modulator outputand drive the antenna. Additionally, a new design of shunt feedbackcurrent reuse common source driver amplifier with resistor and inductorfeedback is proposed to achieve the ultra-wideband bandwidth, high gain,and providing matching for the antenna simultaneously. By properco-design of the modulator, driver amplifier and antenna, the optimumtransmitter performance is achieved.

System Overview

FIG. 1 illustrates a circuit block diagram of a UWB transceiver 100 inaccordance with an embodiment of the present invention. The transceiver100 includes an ultra wideband antenna 105, and receiver componentsincluding a matching network 120, low noise amplifier 130, correlator140, an analog-to-digital converter 150, and data recovery/basebandcircuitry 160, for transmitting and receiving UWB signals. Transmittercomponents include a Gaussian pulse generator 200, UWB modulator 300,and a UWB driver amplifier 400, each of which is further describedbelow. A circulator, diplexer, or switch 110 is used to separate thetransmit and receive signals. Synchronization, clock and control signalsare provided by means of digital backend circuitry 170.

During receiving operation, an UWB signal is received at the UWB antenna105, and supplied to the LNA 130, a broadband impedance matching network120 being used to provide optimal impedance matching between the LNAinput and the antenna. The amplified received signal is subsequentlysupplied to the correlator 140, the correlated output signals beingsubsequently converted to digital signals and the baseband datarecovered therefrom. The digital backend control provides for the clockgeneration, synchronization and data processing.

During a transmitting operation, the Gaussian pulse generator 200receives a clock signal, and responsive thereto, produces an ultrawideband Gaussian pulse. The UWB modulator 300 receives and modulatesthe Gaussian pulse responsive to a received control signal. The UWBdriver amplifier 400 amplifies the UWB modulated signal, simultaneouslyproviding broadband impedance matching to the antenna 105 for optimalpower transfer. The amplified UWB signal is transmitted from the UWBantenna 105 to a remote UWB receiver.

Gaussian Pulse Generator Circuit

FIG. 2 illustrates an exemplary embodiment of the Gaussian pulsegenerator circuit 200 in accordance with the present invention. Thecircuit 200 includes a squaring stage 220, an exponential stage 240, anda second-order derivative stage 260. The squaring function stage 220includes a first transistor 222 having a first terminal 222 a configuredto receive an input signal, a second terminal 222 b coupled to a firstresistor 224, and a third terminal 222 c, whereby the first transistoris configured for biasing in the transistor's saturation region. Such abiasing condition provides the squaring function of the input signal asneeded.

The exponential stage 240 includes a second transistor 242, a thirdtransistor 244, and a second resistor 246. As shown, the secondtransistor 242 has a first terminal 242 a coupled to the firsttransistor's second terminal 222 b, that connection being made via thethird transistor 244. The first terminal 242 a is also coupled to thesecond resistor 246, the second transistor 242 being biased to operatein a sub-threshold region to provide the exponential function of theinput signal. The third transistor 244 is employed to level shift thefirst terminal 242 a of the second transistor to the correct voltage.

The second order derivative stage 260 includes a capacitive-inductivenetwork 262 coupled to the second terminal 242 b of the secondtransistor 242 and an output terminal 264, wherein, when a load R_(L) iscoupled to the output terminal, the real resistance of the load R_(L)combines with the capacitive-inductive network 262 to provide a secondorder derivative response.

The output of the pulse generator can be regarded as a second-orderderivative Gaussian pulse, which can be characterized as:

${V_{out}(t)} \approx {{- {\frac{2k_{e}R_{L}{LCe}^{5{V_{th}/4}}}{\lambda\; V_{th}}\left\lbrack {1 - {\frac{2}{\lambda\; V_{th}}\left( {{V_{i\; n}(t)} - \frac{3V_{th}}{2}} \right)^{2}}} \right\rbrack}}{\mathbb{e}}^{\frac{- {({{V_{i\; n}{(t)}} - \frac{3V_{th}}{2}})}^{2}}{\lambda\; V_{th}}}}$where k_(e) and λ are parameters of the exponential I-V characteristicequation: I_(DS)=k_(e)e^(V) ^(GS) ^(/λ) and are process dependent,V_(th) is the threshold voltage of the first and third (MOSFET)transistors 222 and 244, R_(L) is the load real resistance, and C and Lare respective values of the capacitance and inductance of thecapacitive-inductive network.

In the particular embodiment shown, first and third transistors 222 and244 are n- and p-channel MOSFETs, respectively, and second transistor242 is a bipolar junction transistor. The power plane is provided at+1.8 VDC and signal ground for each of the transistors is groundpotential. An integrated circuit of this arrangement, as will beapparent to those skilled in the art, can be formed using a BiCMOSsemiconductor process. Alternatively, an n-channel device biased foroperation in its sub-threshold region may replace the bipolar transistor242, in which case a corresponding integrated circuit may be fabricatedusing a CMOS semiconductor process.

UWB Modulator Circuit

The Gaussian pulse generator circuit described herein may also be usedwith or incorporated in the design of an ultra wideband modulator.Several types of modulators for UWB transmitters are known in the art,for example, pulse position modulators (PPMs), pulse amplitudemodulators (PAMs), and binary phase shift-keyed (BPSK) modulators.

FIG. 3A illustrates a circuit block diagram of an ultra widebandmodulator circuit 300 in accordance with one embodiment of the presentinvention. The modulator 300 includes a Gaussian pulse generator circuit200 and a modulation control circuit 320. The Gaussian pulse generatorcircuit 200 is configured to receive an input signal 305, which may be aclock signal, and a modulation signal 325 generated from the modulationcontrol circuit 320. The modulation signal 325 is generated as aresponse to a control signal (typically the data to be modulated on theUWB signal) input into the modulation control circuit 320. Responsive tothe modulation signal 325 (which may be a spectrum spreading chipsignal), the pulse generator circuit 200 outputs a modulatedsecond-order Gaussian pulse 350. Several variations of the modulationcontrol circuit 320 are possible, depending upon the desired modulationtype. For example, the modulation control circuit may comprise adouble-pole, single-throw switch that, responsive to a control signal315, is switchable between two modulation states. The two modulationstates may comprise high and low amplitude states in a pulse amplitudemodulation scheme, advanced and delayed states in a pulse positionmodulation scheme, or positive and negative phases in a binary phaseshift keyed modulation scheme. Tertiary, quadrature, or higher orderswitching states are of course possible in other embodiments as well.Further, the pulse generator and modulation control circuits may beseparately designed and fabricated, or formed on a monolithic integratedcircuit.

FIG. 3B illustrates a first embodiment of the ultra wideband modulationcircuit represented in FIG. 3A, the embodiment representing a UWB pulseamplitude modulation circuit 360. The circuit 360 includes a pulsegenerator circuit having squaring, exponential, and second-orderderivative stages 220, 240 and 260, and a modulation control circuit320, as described above. The squaring stage of the pulse generatorcircuit 220 includes a first transistor (e.g., an NMOS FET device)having a first terminal 361 a configured to receive the input signal305, and second and third terminals 361 b and 361 c, respectively. Thesquaring stage 220 further includes a resistor 362 coupled to the secondterminal 361 b of the first transistor 361, the transistor 361 beingconfigured for operation in the saturation region.

The exponential stage 240 includes a second transistor 362 (e.g. a BJT)having a first terminal 362 a coupled to the second terminal 361 b ofthe first transistor 361, that connection being made via a thirdtransistor 363. The third transistor 363 (e.g., a PMOS FET) providessufficient biasing conditions to the second transistor 362, whereby thesecond transistor 362 operates in the sub-threshold region to produce anexponential response. The second-order derivative stage 260 includes acapacitive-inductive network 364 coupled to the second terminal 362 b ofthe second transistor and an output terminal 365, wherein, when a loadR_(L) is coupled to the output terminal 365, the real resistance of theload R_(L) 368 combines with the capacitive-inductive network 364 toprovide a second order derivative response. In the illustratedembodiment as shown, the third terminals 361 c, 362 c, and 363 c of thefirst, second and third transistors are coupled to ground potential.

The modulation control circuit 320 includes transistor 366 having aninput terminal configured to receive the control signal 315 and acurrent mirror 367 coupled to the second transistor 362, whereby theresponsive to the input control signal 315, the current mirror 367produces a modulation signal 325 which alters the biasing condition ofthe second transistor 362. Consequently, the second transistor 362produces a modulated exponential response, which, in combination withthe second order response provided by stage 260, produces a pulseamplitude modulated UWB pulse signal 350. The circuit can be fabricatedas either discrete components or as an integrated circuit. Whenfabricated as an integrated circuit, the illustrated circuit can bemonolithically formed using a BiCMOS semiconductor process.Alternatively, an n-channel device biased for operation in itssub-threshold region may replace the bipolar transistor 362, in whichcase a corresponding integrated circuit may be fabricated using a CMOSsemiconductor process.

FIG. 3C illustrates a second embodiment of the ultra wideband modulationcircuit represented in FIG. 3A, the embodiment representing a UWB binaryphase-shift keyed modulation circuit 370. The circuit 370 includes theaforementioned squaring, exponential and second order derivative stagesof the pulse generator circuit and the modulation control stage 320generally described in FIG. 3A. In this embodiment, the squaring stage220 includes a first transistor M1 having a first terminal M1 a operableto receive the input signal 305 and resistor R1 coupled to the secondport M1 b, the first transistor M1 being biased for operation in thesaturation region. The exponential stage 240 includes, in addition tothe second (BJT) transistor Q1 and third (MOSFET) transistor M2Adescribed in FIG. 3B, fourth transistor Q2 and fifth transistor M2B, thesecond and fourth transistors Q1 and Q2 being arranged as a differentialemitter coupled pair degenerated by inductor L_(CS). Each of the secondand fourth transistors are biased for operation in sub-threshold regionsto provide complementary exponential responses, their bias levels beingset by means of third and fifth transistors M2A and M2B, respectively.

The second-order derivative stage 260 also includes two sections, thefirst capacitive-inductive network (C1 & L1) coupled to the secondterminal of the second transistor Q1, and the secondcapacitive-inductive network (C2 & L2) being coupled to the secondterminal of the fourth transistor Q2. The two capacitive-inductivenetworks are coupled to a common output terminal 372 for connection tothe output load.

The modulation control circuit 320 in this embodiment includes sixth,seventh and eighth transistors M4, M3A and M3B and resistors R3 and R4.When a ramp up signal appears at the first terminal of M1, a Gaussianfunction current flows though the emitter of Q1 then is folded to Q2 bythe tail inductor L_(CS). Hence, two Gaussian function signals(currents) 325 a and 325 b with reverse polarities are achieved. Thesecurrents flow to the capacitive-inductive networks, and then thesecond-order derivative current of Gaussian pulses with reversepolarities are formed at the output of the capacitive-inductivenetworks. Seventh and eighth transistors M3A and M3B are used as twotransmission gates, and are biased by complimentary control voltages.Thus, only one of the modulated currents 325 a or 325 b will passthrough their respective inductive-capacitive networks to the load toform a positive or negative pulse. As can be seen, the polarity ofoutput pulse is determined by the control voltage's level. When level ofthe control signal 315 is high, e.g. representing a positive phase, theoutput pulse is positive, and vice versa for a low signal representing anegative phase. In this manner, the complementary phases of a binaryphase-shift keyed signal are represented in the generated UWB pulse.

As noted with the other circuits, the circuit may be formed either indiscrete components or as an integrated circuit. In the illustratedembodiment in which BJTs and MOSFETs are employed, a BiCMOS process ismost suitable. Alternatively, Q1 and Q2 may be replaced with NMOStransistors configured for sub-threshold biasing, and the circuitfabricated as a CMOS integrated circuit.

Pulse position modulation (PPM) represents another UWB modulationtechnique, whereby a different time lag is used to identify binary 1sand 0s. For example, a long time lag may be used to represent a 1 bitand a short time lag may represent a 0 bit. As indicated in the pulsegenerator circuit, the pulse is generated by the edge of the input(typically clock) signal. To generate PPM pulses, the edge location ofthe input clock signal is modulated by the information data (controlsignal), and subsequently the edge location modulated pulses can bepassed through a pulse generator to produce PPM pulses.

FIG. 3D illustrates the performance of a BPSK modulator constructed inaccordance with the present invention. When the input control voltage isin low level (for example 0V), M3A and M4 is off and M4B is on, thus theGaussian pulse with positive polarity is output. On the other hand, whenthe input control voltage is in high level (for example 1.8V), M3A ison, M4 and M4B is off, thus the Gaussian pulse with negative polarity isoutput.

UWB Driver Amplifier Circuit

FIG. 4A illustrates an ultra wideband driver amplifier in accordancewith one embodiment of the present invention. The UWB driver amplifieris used to amplify the modulated UWB pulse, as well as to provide abroadband impedance match between the modulator and the antenna.

As shown in FIG. 4A, the UWB driver amplifier 400 includes one or moreamplifier stages 420, each amplifier stage including parallel coupledfirst and second amplifier stage transistors 422 and 424. Each of theamplifier stage transistors 422 and 424 has first, second, and thirdterminals, wherein the first (e.g., gate) terminals 422 a and 424 a arecoupled together to form a first node 425, and the third (drain)terminal 422 c of the first transistor and the second (drain) terminal424 b of the second transistor are coupled together at a second node429. Coupled between the first and second nodes 425 and 429 is aninductive-resistive network 426 which provides shunt feedback. Inessence, each stage is configured as a shunt feedback common sourceamplifier stage with resistor and inductor feedback, in which PMOS-NMOScurrent reuse technique is employed to improve the gm and gain withoutsacrificing the bandwidth.

One or more of the amplifier stages may be used to provide sufficientsignal gain for transmission. Three cascaded stages are shown in theillustrated embodiment, although fewer or more stages may be used inalternative embodiments. Preferably, the gate peripheries of the firstand second transistors 422 and 424 are substantially the same, althoughdifferent gate peripheries may be employed in alternative embodiments.Additionally, each amplifier stage may have the same total periphery, oralternatively, different stages may have different total gateperipheries, depending upon the design technique. For example, in oneembodiment the UWB drive amplifier may employ amplifier stages ofsuccessively increasing gate peripheries in order to provide a higherlinear output power (IP3) characteristic. In another embodiment, the UWBdriver amplifier may employ amplifier stages of substantially the samegate periphery to provide an extremely wide impedance match. These andother design approaches may be adopted in amplifier's architecture.

Further included in the exemplary UWB driver amplifier embodiment areinput and output capacitors 420 and 430, the values of which may beselected to provide DC blocking and/or AC coupling, the latter beingused to attenuate any output signals below the USB spectrum low end (3.1GHz in the US) to a sufficient degree in order to comply with UWB signalemission regulations.

Additionally, it is well known that the position of the poles and zerosdetermine the bandwidth and gain of the amplifier. The bandwidth of theUWB driver amplifier is improved by using dominant pole bandwidthenhancement technique which can increase the bandwidth withoutcompromising gain. The small signal equivalent circuit analysis of eachstage amplifier shows reveals 2 zeros and 3 poles. Among them, two zerosand two poles remain close to the origin, but the position of thedominant pole is very far away from the origin. This pole arrangementhelps to increase the bandwidth of the amplifier without compromising ongain.

In a specific embodiment, a three-stage UWB driver amplifier wasdesigned using 0.18 um CMOS technology. Biasing conditions weresimulated at 1.8V @ 18 mA. The performance parameters are summarized inTable I below.

TABLE I Property Value −3 dB bandwidth 2.2-10.1 GHz S(1, 1) −2.5 to 3.6dB in 2.2-10.1 GHz S(1, 2) <−46 dB in 2.2-10.1 GHz S(2, 1) or Power gain21 dB in 2.2-10.1 GHz S(2, 2) <−5 dB in 2.2-10.1 GHz IIP3 −8 dBm OutputNF @ 50 Ohm <3.5 dB in 2.2-10.1 GHz Voltage Gain 15 dB in 2.2-10.1 GHzI@V 18.4 mA @ 1.8 V Stability Factor, K >7.8 in 2.2-10.1 GHz Stabilitymeasurement >1.0 in 2.2-10.1 GHzUWB Transmitter

FIG. 5A illustrates a simplified block diagram a transmitter circuitconstructed in accordance with the present invention. The particulartransmitter employs pulse amplitude modulation to communicate basebanddata, although BPSK, PPM or any type of modulation technique may be usedin accordance with the present invention.

As shown in FIG. 5A, an input signal 305 and control signal 315 aresupplied to a UWB pulse amplitude modulator 510, an exemplary embodimentof which is shown in FIG. 3B. The pulse amplitude modulator 510 outputsGaussian pulses 520, the amplitude of which is modulated by the level ofthe control signal 315. The modulated Gaussian pulse 520 is supplied tothe driver amplifier circuit 530, an exemplary embodiment of which isshown in FIG. 4. The driver amplifier outputs an amplified Gaussianpulse 535, and additionally provides broadband matching to the UWBantenna 550 gain for maximum power transfer and UWB signal transmissionefficiency.

FIG. 5B illustrates the input/clock, control/modulation and output pulsesignals of an UWB transmitter employing the pulse amplitude modulator ofFIG. 3B and the driver amplifier circuit shown in FIG. 4. Theinput/clock signal generates the UWB Gaussian pulse. Thecontrol/modulation signal controls the amplitude of the pulse. At theantenna output, a high amplitude Gaussian pulse with a peak to peakvoltage of 142 mV to −80 mV is generated by a high control signalvoltage and a low amplitude Gaussian pulse with a peak to peak voltageof 79 mV to −50 mV is generated by a low control voltage.

As shown, a serial data stream of 1 0 1 0 is transmitted. A highamplitude UWB Gaussian pulse is generated when a digital “1” istransmitted and a low amplitude UWB Gaussian pulse is generated when adigital “0” is transmitted. Advantageously, the system simulationindicated that even with additional distortion applied to the signalafter transmission, the demodulation performance was not affectedsignificantly when the receiving and transmitting antennas aresubstantially the same. The power consumption of the PAM UWB transmitteris 0.043 W.

The foregoing description has been presented for purposes ofillustration and description. It is not intended to be exhaustive or tolimit the invention to the precise form disclosed, and obviously manymodifications and variations are possible in light of the disclosedteaching. The described embodiments were chosen in order to best explainthe principles of the invention and its practical application to therebyenable others skilled in the art to best utilize the invention invarious embodiments and with various modifications as are suited to theparticular use contemplated. It is intended that the scope of theinvention be defined by the claims appended hereto.

1. A Gaussian pulse generator circuit, comprising: a squaring stage, comprising a first transistor having first, second and third terminals and configured to operate in the saturation region; an exponential stage, comprising a second transistor having a first terminal coupled to the second terminal of the first transistor, a second terminal, and a third terminal, the second transistor configured to operate in the sub-threshold region; and a second-order derivative stage, comprising an capacitive-inductive network coupled to the second terminal of the second transistor, and an output terminal, wherein, when a load is coupled to the output terminal, the real resistance of the load combines with the capacitive-inductive network to provide a second order derivative response.
 2. The Gaussian pulse generator circuit of claim 1, wherein the squaring stage further comprises a first resistor coupled to the second terminal of the first transistor.
 3. The Gaussian pulse generator circuit of claim 1, wherein the exponential stage further comprises: a second resistor coupled to the first terminal of the second transistor; and a third transistor having a first terminal coupled to the second terminal of the first transistor, a second terminal coupled to the first terminal of the second transistor, and a third terminal.
 4. The Gaussian pulse generator circuit of claim 3, wherein the first and third transistors comprise MOSFET transistors, and the second transistor comprises a BJT transistor.
 5. The Gaussian pulse generator circuit of claim 3, wherein the first, second, and third transistors comprise MOSFET transistors.
 6. The Gaussian pulse generator circuit of claim 1, wherein an output voltage is calculated as: ${V_{out}(t)} \approx {{- {\frac{2k_{e}R_{L}{LCe}^{5{V_{th}/4}}}{\lambda\; V_{th}}\left\lbrack {1 - {\frac{2}{\lambda\; V_{th}}\left( {{V_{i\; n}(t)} - \frac{3V_{th}}{2}} \right)^{2}}} \right\rbrack}}{\mathbb{e}}^{\frac{- {({{V_{i\; n}{(t)}} - \frac{3V_{th}}{2}})}^{2}}{\lambda\; V_{th}}}}$ where k_(e) and λ are parameters of the exponential I-V characteristic equation: I_(DS)=k_(e)e^(V) ^(GS) ^(/λ), R_(L) is the load real resistance, and C and L are respective values of the capacitance and inductance of the capacitive-inductive network.
 7. The Gaussian pulse generator circuit of claim 1, wherein the circuit is an integrated circuit monolithically formed using a BiCMOS semiconductor process.
 8. The Gaussian pulse generator circuit of claim 1, wherein the circuit is an integrated circuit monolithically formed using a CMOS semiconductor process.
 9. An ultra wideband modulator circuit, comprising: a Gaussian pulse generator circuit, comprising: a squaring stage, comprising a first transistor having first, second and third terminals, the first transistor configured to receive an input signal at the first terminal and to operate in the saturation region; an exponential stage, comprising a second transistor having a first terminal coupled to the second terminal of the first transistor, a a second-order derivative stage, comprising a first capacitive-inductive network coupled to the second terminal of the second transistor, and an output terminal, wherein, when a load is coupled to the output terminal, the real resistance of the load combines with the first capacitive-inductive network to provide a second order derivative response; and a modulation control circuit having an input configured to receive a control signal and an output coupled to the Gaussian pulse generator circuit, the modulation control circuit configured to modulate the biasing condition of the exponential stage as a function of the input control signal.
 10. The ultra wideband modulator circuit of claim 9, wherein the squaring stage further comprises a first resistor coupled to the second terminal of the first transistor.
 11. The ultra wideband modulator circuit of claim 9, wherein the exponential stage further comprises a third transistor having a first terminal coupled to the second terminal of the first transistor, a second terminal coupled to the first terminal of the second transistor, and a third terminal.
 12. The ultra wideband modulator circuit of claim 11, wherein the modulation control circuit comprises: a fourth transistor having a control port for receiving a control signal, a first port and a second port; and a current mirror circuit having a first port coupled to the first port of the fourth transistor, a second port coupled to the control port of the second transistor, and a third port coupled to the inductor-capacitor network.
 13. The ultra wideband modulator circuit of claim 12, wherein the first, third and fourth transistors each comprise a MOSFET transistor, and the second transistor comprises a BJT transistor.
 14. The ultra wideband modulator circuit of claim 12, wherein each of the first, second, third and fourth transistors comprise a MOSFET transistor, and wherein the circuit is an integrated circuit monolithically formed using a CMOS process.
 15. The ultra wideband modulator circuit of claim 11, wherein the exponential stage further comprises: a fourth transistor having a first terminal coupled to the third terminal of the first transistor, a second terminal, and a third terminal coupled to the third terminal of the second transistor; and a fifth transistor having a first terminal coupled to the second terminal of the second transistor, a second terminal coupled to the third terminal of the first transistor, and a third terminal; wherein the second and fourth transistors operate in a differential manner.
 16. The ultra wideband modulator circuit of claim 15, wherein the second order derivative circuit further comprises a second-order derivative stage coupled to the second terminal of the second transistor and to the output terminal, wherein, (i) when a load is coupled to the output terminal and the second transistor is conducting, the real resistance of the load combines with the first capacitive-inductive network to provide a second order derivative response, and (ii) when a load is coupled to the output terminal and the fourth transistor is conducting, the real resistance of the load combines with the second capacitive-inductive network to provide a second order derivative response.
 17. The ultra wideband modulator circuit of claim 16, wherein the modulation control circuit comprises: a sixth transistor having a first terminal configured to receive the control signal, a second terminal and a third terminal; a seventh transistor interposed between the first capacitive-inductive network and the output terminal, the seventh transistor having a first terminal coupled to the first terminal of the sixth transistor, a second terminal coupled to the first capacitive-inductive network and a third terminal coupled to the output terminal; and an eighth transistor interposed between the second capacitive-inductive network and the output terminal, the eighth transistor having a first terminal coupled to the second terminal of the seventh transistor, a second terminal coupled to the output terminal, and a third terminal coupled to the second capacitive-inductive network.
 18. The ultra wideband modulator circuit of claim 17, wherein the first, third, fifth, sixth and seventh transistors are MOSFET transistors and the second and fourth transistors are BJT transistors.
 19. The ultra wideband modulator circuit of claim 18, wherein the circuit is an integrated circuit monolithically formed using a BiCMOS semiconductor process.
 20. The ultra wideband modulator circuit of claim 9, wherein the circuit is an integrated circuit monolithically formed using a BiCMOS process.
 21. An ultra wideband transmitter circuit, comprising: an ultra wideband modulator circuit, comprising: a squaring stage, comprising a first transistor having first, second and third terminals and configured to operate in the saturation region; an exponential stage, comprising a second transistor having a first terminal coupled to the second terminal of the first transistor, a second terminal, and a third terminal, the second transistor configured to operate in the sub-threshold region; a second-order derivative stage, comprising an capacitive-inductive network coupled to the second terminal of the second transistor, and an output terminal; and a modulation control circuit having an input configured to receive a modulation control signal and an output coupled to the Gaussian pulse generator circuit, the modulation control circuit configured to modulate the biasing condition of the exponential stage as a function of the modulation control signal; and a driver amplifier having an input coupled to the output terminal of the second-order derivative stage and an output, the driver amplifier providing the real resistance component to the capacitive-inductive network to produce a second-order derivative signal at the driver amplifier input, the driver amplifier comprising one or more serial-coupled amplifier stages, wherein each amplifier stage comprises: parallel coupled first and second amplifier stage transistors, each of the first and second amplifier stage transistors having first, second and third terminals, wherein the first terminals of the first and second amplifier stage transistors are coupled together at a first node, and the third terminal of the first amplifier stage transistor and the second terminal of the second amplifier stage transistor are coupled together at a second node; and a feedback network coupled between the first and second nodes, the feedback network comprising an inductive element and a resistive element.
 22. The ultra wideband transmitter circuit of claim 21, wherein the squaring stage further comprises a first resistor coupled to the second terminal of the first transistor.
 23. The ultra wideband transmitter circuit of claim 21, wherein the exponential stage further comprises a third transistor having a first terminal coupled to the second terminal of the first transistor, a second terminal coupled to the first terminal of the second transistor, and a third terminal.
 24. The ultra wideband transmitter circuit of claim 23, wherein the modulation control circuit comprises: a fourth transistor having a control port for receiving a modulation control signal, a first port and a second port; and a current mirror circuit having a first port coupled to the first port of the fourth transistor, a second port coupled to the control port of the second transistor, and a third port coupled to the inductor-capacitor network.
 25. The ultra wideband transmitter circuit of claim 24, wherein the first, third and fourth transistors each comprise a MOSFET transistor, and the second transistor comprises a BJT transistor.
 26. The ultra wideband modulator circuit of claim 21, wherein the exponential stage further comprises: a fourth transistor having a first terminal coupled to the third terminal of the first transistor, a second terminal, and a third terminal coupled to the third terminal of the second transistor; and a fifth transistor having a first terminal coupled to the second terminal of the second transistor, a second terminal coupled to the third terminal of the first transistor, and a third terminal; wherein the second and fourth transistors operate in a differential manner.
 27. The ultra wideband transmitter circuit of claim 26, wherein the second order derivative circuit further comprises a second-order derivative stage coupled to the second terminal of the second transistor and to the output terminal, wherein, (i) when a load is coupled to the output terminal and the second transistor is conducting, the real resistance of the load combines with the first capacitive-inductive network to provide a second order derivative response, and (ii) when a load is coupled to the output terminal and the fourth transistor is conducting, the real resistance of the load combines with the second capacitive-inductive network to provide a second order derivative response.
 28. The ultra wideband transmitter circuit of claim 27, wherein the modulation control circuit comprises: a fifth transistor having a first terminal configured to receive the modulation control signal, a second terminal and a third terminal; a sixth transistor interposed between the first capacitive-inductive network and the output terminal, the sixth transistor having a first terminal coupled to the first terminal of the fifth transistor, a second terminal coupled to the first capacitive-inductive network and a third terminal coupled to the output terminal; and a seventh transistor interposed between the second capacitive-inductive network and the output terminal, the seventh transistor having a first terminal coupled to the second terminal of the fifth transistor, a second terminal coupled to the output terminal, and a third terminal coupled to the second capacitive-inductive network.
 29. The ultra wideband transmitter circuit of claim 21, further comprising a capacitor having a first port for receiving an input signal and a second port coupled to the first node of the first of the one or more amplifier stages.
 30. The ultra wideband transmitter circuit of claim 29, further comprising a capacitor having a first port coupled to second node of the last of the one or more amplifier stages and a second port for providing an output signal.
 31. The ultra wideband transmitter circuit of claim 21, wherein the gate periphery of the first and second amplifier stage transistors within the same amplifier stage is substantially matched.
 32. The ultra wideband transmitter circuit of claim 21, wherein the first and second amplifier stage transistors of different amplifier stages are of different gate peripheries.
 33. The ultra wideband transmitter circuit of claim 21, wherein the first and second amplifier stage transistors of the different amplifier stages are of substantially the same gate peripheries.
 34. The ultra wideband transmitter circuit of claim 21, wherein the circuit is an integrated circuit monolithically formed using a BiCMOS process.
 35. The ultra wideband transmitter circuit of claim 21, wherein the circuit is an integrated circuit monolithically formed using a CMOS process. 